1. Field of the Invention
The present invention relates to electrostatic discharge (ESD) protection in semiconductor devices, in particular in semiconductor devices in which an input or output signal of the device is permitted to vary within a predetermined range of potentials including a potential equal or close to the potential of one of the power supply lines of the device.
2. Description of the Related Art
FIG. 1 of the accompanying drawings shows parts of a conventional semiconductor device having ESD protection. An output circuit 2 of the device generates an output signal V.sub.O, which is output from the device at an output terminal 3 thereof. The output voltage is permitted to vary within a range from 0 to +1 volts (relative to electrical ground GND) when the device is in use.
To protect the device 1 from damage caused by electrostatic discharges, for example due to accidental touching of the output terminal 3 by an assembly worker during assembly of the device onto a printed circuit board, the device is provided with ESD protection circuitry comprising respective first and second metal-oxide-semiconductor (MOS) field-effect-transistors (FETs) 4 and 5. The first MOS transistor 4 is of the P-type conductivity and has its gate and its source region connected to a positive power supply line VDD of the device and its drain region connected to the output terminal 3.
The second MOS transistor 5 is of the N-type conductivity and has its drain region connected to the output terminal 3 and its gate and its source region connected to a negative supply line of the device (electrical ground GND).
When the device is in use, for example when it is assembled on a circuit board and powered up, both the first and second MOS transistors 4 and 5 are turned OFF so as not to affect the circuit operation. If, however, the potential of the output terminal becomes sufficiently positive with respect to the positive supply line VDD, the transistor 4 turns ON and conducts current safely from the output terminal 3 to the positive supply line VDD, thereby preventing damage to the internal circuitry of the device such as the output circuit 2. Similarly, if the output-terminal potential becomes sufficiently negative with respect to electrical ground, the second MOS transistor 5 turns ON, so as to safely conduct current from the GND line to the output terminal 3.
As shown schematically in FIG. 1, although each of the transistors 4 and 5 for ESD protection is normally OFF during operation of the device, each transistor 4 and 5 can be regarded as having respective diodes associated with its source and drain regions. In the case of the PMOS transistor 4, there is a "source diode" D.sub.SP effectively connected between the source region and VDD and a "drain diode" D.sub.DP effectively connected between the drain region and VDD.
In the case of the NMOS transistor 5, there are respective source and drain diodes D.sub.SN and D.sub.DN, effectively connected between the relevant source or drain region and GND.
All of the diodes D.sub.DP, D.sub.SP, D.sub.DN and D.sub.SN are normally non-conducting, since none of them is forward biased so long as the output-terminal potential V.sub.O remains within its permitted range of from 0 to +1 volts. However, two problems arise in the FIG. 1 device from the presence of the NMOS transistor 5. Firstly, the drain diode D.sub.DN provided by the NMOS transistor 5 may become sufficiently forward biased if the output-terminal potential V.sub.O goes below 0 volts. The NMOS transistor 5 therefore has the effect of limiting the permitted range of output voltages of the output circuit 2, which in certain applications (for example digital-to-analog converters having current outputs) may be undesirable.
Secondly, the drain diode D.sub.DN provided by the NMOS transistor 5, although turned OFF, has a parasitic capacitance associated with it and this capacitance is both relatively large and highly non-linear when the output-terminal potential is within the permitted range close to GND. By way of illustration, a curve N in FIG. 2 shows the variation of the parasitic capacitance associated with the NMOS transistor 5 with the output-terminal potential V.sub.O. In FIG. 2, VDD is 3V, by way of example. When the output-terminal voltage V.sub.O is within the range of from 0 to +1 volts, it can be seen from FIG. 2 that the effect of the parasitic capacitance associated with the N MOS transistor 5 can be highly significant.
Incidentally, for comparison purposes, the corresponding parasitic capacitance associated with the PMOS transistor 4 is indicated by a curve P. The parasitic capacitance associated with the PMOS transistor 4 is relatively low and, moreover, relatively linear. Such linearity makes it possible to compensate for the parasitic capacitance of the PMOS transistor, if desired. No such compensation is possible, however, for the much larger parasitic capacitance associated with the NMOS transistor 5, in view of the non-linearity thereof.
It is therefore desirable to provide ESD protection for a semiconductor device which does not impose restrictions of the kind mentioned above on the permitted range of input/output voltages of the device and also avoids the problems associated with parasitic capacitances of the ESD protection circuitry.